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sh3002 microbuddy? reset management and clock management support ic for microcontrollers system management 2005-08-08 copyright ?2002-2005 semtech corporation 1 sh3002 data sheet v1.20 www.semtech.com description the programmable sh3002 microbuddy? (buddy?) provides mandatory microcontroller support functions: ? cpu supervisor ? clock management system ? auxiliary functions three components make a complete system: any microcontroller, the sh3002, and a bypass capacitor. this low-cost system would consume very little power and have clock-frequency accuracy of 0.5%. the sh3002 can operate completely stand-alone, or under control of the microcontroller. a single-wire interface handles both bi-directional communications and the interrupt / wake-up signal from the sh3002. the sh3002 stores all configurati on, calibration, parameters, and status information in a 36-byte bank of control registers. on reset, most of these are reloaded with defaults from the factory-set nonvolatile memory. the microcontroller can change any settings on the fly. if some of the settings must remain fixed, a comprehensive set of write-protect bits is provided for several related groups of registers (with both permanent write-inhibit and lock/unlock capabilities). applications ? home automation and security ? consumer products ? portable/handheld computers ? industrial equipment ? any microcontroller-based product features ? highly integrated ic - 3 mm x 3 mm x 0.9 mm 16-lead mlp (qfn) package ? cpu supervisor - low v dd reset programmable from 2.3 v to 4.3 v - both active-high and active-low reset outputs ? clock management system - replaces high-frequency (hf) crystal or resonator - programmable clock output from 32.768 khz to 16 mhz - speed shift between multiple clock frequencies - adjustable spectrum spreading for emi reduction - directly supports microcontroller stop function - deep sleep with instantaneous auto-wakeup ? operates from 2.3 v to 5.5 v - ideal for battery-operated devices ? i dd <850 a / 2 mhz, <3 ma / 16 mhz, <10 a / standby pin configuration 3mm mlp (qfn) package sh3002 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 v ss v reg v dd nc nc nc v ss v ss r ref n rst t est (v ss ) rst clk32 io/i nt clk in clk out typical application circuit sh3002 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 c ontroller v dd x in x out gpio with int n reset g nd v+ c bypass covered by us patent no. 6,903,986 semtech, the semtech logo, microbuddy, buddy, and b are marks of semtech corporation. all other marks belong to their respective owners.
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 2 v1.20 www.semtech.com description ordering information sh3002imltr ic mlp 3 x 3 mm, 16 pins, temp. range -40 c to +85 c evk-sh3000usb sh3000 evaluation kit sh3000ek.pdf sh3000 evaluation kit user guide SH3000UM.pdf sh3000 reference manual block diagram clk32 microcontroller v+ v dd 32.768 k h z x in x out r eset i/o pin v ss nc v reg lf oscillator reset drivers & logic v dd monitor hf oscillator & fll periodic interrupt / wake-up timer rc oscillator regulators nonvolatile memory calibration & default settings serial i/o control logic 8 clock driver & start/stop logic post-scaler 2 3 4 9 10 11 12 5 6 7 13 14 15 16 interrupt v dd v ss nc nc voltage reference clk out clk in r ref rst n rst t est io/i nt sh3002 buddy? 1 v ss
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 3 v1.20 www.semtech.com pin descriptions pin name type function 1 v ss power ground, 0 v. all v ss pins and t est (v ss ) pin must be connected together. 2 v reg power output of internal voltage regulator, 2.2 v nominal. this pin can power external loads of <5 ma. if load is ?noisy? it requires a bypass capacitor. may be left unconnected or used as a high logic level signal for clk sel pin (see below). 3 v dd power main power supply, +2.3 to +5.5 v. 4 nc not connected - reserved 5 nc not connected - reserved 6 nc not connected - reserved 7 v ss power ground, 0 v. all v ss pins and t est (v ss ) pin must be connected together. 8 v ss power ground, 0 v. all v ss pins and t est (v ss ) pin must be connected together. 9 r ref analog optional 1 mohm external bias resistor fo r the internal 32.768 khz rc oscillator. can be used to set, trim or modulate the internal rc oscillator. keep open if not used. 10 n rst digital out a ctive low system reset output. asserted wi th a strong low state when a reset condition occurs. weakly pulled to v dd internally when not active. this signal is valid for v dd as low as 1 v. keep open if not used. 11 rst digital out active high system reset output. asserted with a strong high state when a reset condition occurs. weakly pulled to v ss internally when not acti ve. this signal is valid for v dd as low as 1 v. keep open if not used. 12 t est (v ss ) digital in factory test enable. all v ss pins and t est (v ss ) pin must be connected together. 13 clk32 digital out buffered internal 32.768 khz clock, derived according to the clk sel pin setting. this pin uses backup power for the buffer when v dd is not present. when driving high, this signal is either at v bak or v dd (if v dd is higher than the reset threshold). when enabled, this signal runs continuously independent of clk out activity. minimize the external load to reduce power consumption during backup operati ons. when disabled, this pin is driven to v ss . keep open if not used. 14 io/i nt i/o serial communications interface and interrupt out put pin. this pin is internally weakly pulled to the opposite of the programmed interr upt polarity. for example, if interrupt is programmed to be active low, this pin is weakly pulled to v dd when inactive. keep open if not used. 15 clk in digital in clock activity sense input. used to detect when the target microcontroller enters stop mode (which disables its clock). connect to the microcontroller?s clock output or oscillator output pin. connect to v ss when not used. clk in must not be left open. 16 clk out digital out programmable high frequency clock output. connect to the target microcontroller?s clock input or oscillator input pin. k eep open if not used.
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 4 v1.20 www.semtech.com functional description the sh3002 is a single-chip support system for microcontrollers, microprocessors, dsps and asics. it consists of four major functional blocks, each block having numerous enhancem ents over alternative solutions. the major modules are the cpu supervisor, the clock management system, and the auxiliary functions. the entire chip is controlled by the set of internal registers and accessed via the si ngle-pin serial interface. all of the settings, configuration, and calibration or operating parameters are programmable and re- programmable at any time. all of the parameters required for stand-alone operations are initialized on reset from the built-in factory-programmed nonvolatile memory. this allows the sh3002 to operate autonomously for most of its supervisory functions. the stand-alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential benefit of the sh3002 might not be realized. in the preferred configuration, where the sh3002 is tightly coupled to the target micro, the sh3002 offers an unprecedented level of design flexibility in clock and power usage management. the sh3002 is a particularly desirable integration because the built-in features interact and meld to produce more useful system level functions. for example, on power up, the sh3002 can quickly release the reset lines on its cpu supervisor module because the clock signal from the clock management system is guaranteed to be running and stabilized. an ordinary reset circuit must hold reset active for a long time to allow an unknown crystal to start up and stabilize. the sh3002 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as necessary with no external support. the clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. users should consider the interactions of the major functional blocks to gain the maximum advantage from the sh3002. the individual functional blocks are described in the following sections.
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 5 v1.20 www.semtech.com cpu supervisor the sh3002 has two supervisory functions that manage the reset of the target processor, a low v dd monitor (brownout detector), see figure 1 . both functions are integrated with the clock management system to provide a more complete system solution than stand-alone components. the sh3002 has both active high and active low reset output pins. both are driven strong to the active state and weak to the inactive state. this eliminates the need for external pull-ups and allows various reset sources to be connected together in a wire-or configuration. (this makes it simple to set up a manual reset circuit.) a set of flags in the register map indicates the source of the reset to the system software. low v dd reset the sh3002 drives the reset pins active whenever v dd is below the value of v bo , the brownout reset threshold, programmable from 2.3 v to 4.3 v in average steps of 33 mv, see table 1 . table 1. programmable v bo values parameter min typ max units vbo for min code (000000) 2.27 2.3 2.33 v vbo for max code (111111) 4.2 4.3 4.4 v step resolution 33 mv the default v bo value is loaded on power-up from the factory-programmed nonvolatile memory. it can be re- programmed at any time or it can be permanently protected from any changes by setting the v bo lock flag or a write-protect flag. on power up both the active-high and active-low reset signals are driven active. these outputs are typically valid for a v dd level of at least 0.5 v, and guaranteed to be valid for a v dd level of 1.0 v. the reset outputs remain active until v dd rises and stays above the level of (v bo + v hyst ), where v hyst is a small fixed amount of hysteresis, nominally 50 mv, added to prevent nuisance reset activations (when v dd slowly changes near the level of v bo and some noise or power glitching is present). at the level of (v bo + v hyst ) the power supply is considered valid. in case of the initial power-up, the reset is then driven inactive once 6 ms of valid power have elapsed. in the case of brownout, the reset is released after a delay of 6 ms (but no less than 12 ms from the beginning of the brownout). such a fast reset is possible because the sh3002 provides a fast-starting clock t hat is free of crystal start- up time requirements. this gives the sh3002 an advantage over most external reset circuits, which must have a long reset pulse duration to accommodate long and unpredictable crystal start-up times. the sh3002 guarantees that a valid and stable clock is available 2 ms before the reset signals are negated, so that internal synchronous reset and initialization of the target micro can proceed normally. figure 1. cpu supervisor --- low v dd / brownout detector, watchdog, reset logic & drivers noise filter 1 v dd v high v low threshold d/a 4.40 v 2.30 v hysteresis 50mv typ . reset logic & minimum duration timer pwr ok temperature- compensated voltage reference 10 n rst 11 rst v dd 20 k 20 k u nderflow 1 0 32.768kh z 6-bit value from / to serial i/o write-once initialization logic lock logic r eset r eset
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 6 v1.20 www.semtech.com since the clock is only active for the last 1 or 2 ms of the reset interval, when v dd has already been valid for some time, energy savings are realized and the startup of the whole system is made easier. the commonly used reset approach forces the processor to turn the oscillator on and to run at full speed (thus consuming full power) during the critical time when the (possibly depleted) battery is trying to raise v dd to an acceptable level. in contrast, the sh 3002 allows the power source to charge the bypass capacito rs and raise the level of v dd with little additional load. only when power has stabilized is the target micro permitted to start expending energy. when a brownout event occurs, the sh3002 continues to provide the cloc k to the target processor, but at a reduced frequency between 500 khz and 1.0 mhz. after a delay of 2 ms this clock is stopped, automatically lowering the energy consumption of the whole system, see figure 2. a noise filter (see figure 1 ) prevents reset activations from noise and small power glitches on the v dd line. a typical behavior is shown in figure 3 for the v dd level just above v bo and various amplitudes and durations of the negative-going spikes. when v dd is falling, both reset lines are guaranteed to activate within 5 s from the time v bo is crossed over. v dd rst n rst clk out figure 2. operations of low v dd / brownout detector 1v v bo v bo + v hyst 3-5ms 12ms minimum 2 ms 2 ms 1 ms undefined normal f out reduced f out 0.5-1.0 mhz 6ms 0 5 10 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 am plitude, v duration, s guaranteed no reset guaranteed reset duration amplitude figure 3. response to negative voltage spikes
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 7 v1.20 www.semtech.com clock management system the sh3002 provides a flexible tool for creating and managing clocks, a versatile and accurate ?any frequency? clock synthesizer (see figure 4 ). it is capable of generating any frequency in the range of 62.5 khz to 16.0 mhz, with worst-case resolution of 0.0256% (256 ppm). the internal 32.768 khz clock can also be routed to the clk out pin (and hf oscillator stopped for energy savings). the objectives, features, and behavior of the clock management system are aimed towards the systems that utilize a microcontroller, a microprocessor, a dsp or an asic. the sh3002 permits the automatic sensing of the intentions of the host processor, an industry first. the sh3002 shuts down its clock ou tput when it senses that the host processor issued a stop instruction. subsequently, the sh3002 idles, consuming less than 10 a. as soon as the host exits the stop mode, the sh3002 instantaneously starts to supply a stable clock (<2 s wake-up). a typical system, constructed with a ceramic resonator or a crystal as the frequency determining element, must wait at least several hundred microseconds (for a resonator), or as much as 100 ms or more (for a hf crystal), to re-start the oscillator. the sh3002 allows the response to and service of an event to finish with a speed previously unattainable for a simple microprocessor. a system with a traditional clock approach can be as much as 100x ? 10,000x slower. clock generator operation the frequency synthesizer in the sh3002 is constructed from the 2:1 tunable 8.0?16.0 mhz hf oscillator followed by a pr ogrammable ?power-of-two? post-divider (see figure 4 ). the clock source selector and the programmable post-scale divider allow instantaneous switching between the 32.768 khz internal clock and divided-down hf oscillator output. there is no settling or instability when the switch occurs. this is a preferred method for clock control in computing systems, when the large ratio between high and low frequency of operations allows for correspondingly large and instantaneous savings in power consumption. when the hf oscillator is operating alone, it can set the frequency of the clock on the clk out pin to 0.025%, and maintain it to 0.5% over temperature. this compares favorable with the typical 0.5% initial clock accuracy and 0.6% overall temperature stability of ceramic resonators. the sh3002 replaces the typical resonator, using less space and providing better performance and functionality. the hf oscillator can also be locked to the internal 32.768 khz signal. the absolute accuracy and stability of the hf clock depends on the quality of the 32.768 khz internally generated clock; the low-frequency (lf) oscillator system is described later in this document. post-scaler (divide by 1, 2, 4, 8, 16, 32, 64, 128) figure 4. simplified hf oscillator system 32.768 khz s tart /s top 16 15 clk out clk in clock buffer and glue logic hf digitally controlled oscillator 8-16 mhz 18-bit dco code register clock on force dco on clock source 1 0 spectrum spreading controls frequency locked loop logic 13-bit frequency set value 16 2048 hz 8-bit pseudo random noise generator fll on from / to serial i/o
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 8 v1.20 www.semtech.com the sh3002 employs a frequency locked loop (fll) to synchronize the hf clock to the 32.768 khz reference. this architecture has several advantages over the common pll (phase locked loop) systems, including the ability to stop and re-start without frequency transients or instability, and with instant settling to a correct frequency. the conventional pll approach invariably includes a low-pass filter that requires a long settling time on re-start. the primary purpose of the fll is the maintenance of the correct frequency while the ambient temperature is changing. as the temperature drift of the hf oscillator is quite small, any corrective action from the fll system is also small and gradual, commensurate with the temperature variation. the fll system in the sh3002 is unconditionally stable. to set a new frequency for the fll, the host processor writes the 13-bit frequency set value. the resulting output frequency is calculated using simple formulas [1] and [2] (reference frequency is 32.768 khz): f osc = 2048 hz * (frequency set value + 1) [1] f out = f osc / (post-divider setting) [2] for example, a post-divider setting of 8 and the frequency set value of 4000 (0x0fa0) produce an output frequency of 1.024 mhz. programmable spectrum spreading most commercial electronic systems must pass regulatory tests in order to determine the degree of their electromagnetic interference (emi) affecting other electronic devices. in some cases compliance with the emi standards is costly and complicated. the sh3002 offers a technique for reducing the emi. it can be a part of the initial design strategy, or it can be applied in the prototype stage to fix problems identified during compliance test ing. this feature of the sh3002 can greatly reduce the requirements for radiofrequency shielding, and permits the use of simple plastic casings in place of expensive rfi-coated or metal casings. the sh3002 employs programmable spectrum spreading in order to reduce the rf emissions from the processor?s clock. there are five (5) possible settings; please see table 2 for operating and performance figures in the 8-16 mhz range. spectrum spreading is created by varying the frequency of the hf oscillator with a pseudo-random sequence (with a zero-average dc component). the maximum-length sequence (mls) 8-bit random number generator, clocked by 32.768 khz, is used. only 4, 5, 6, or 7 bits of the generated 8-bit random number are used, according to the configuration setting. maximum fluctuations of the frequency depend on the selected frequency range and the position within the range. selecting the hf oscillator frequency to be near the high end of the range limits the peak variations to 0.1%, 0.2%, 0.4%, or 0.8% (corresponding to the configuration setting). special operating modes the sh3002 can operate stand-alone, without connections to the in and out terminals of the host?s oscillator. for example, a bank of sh3002 chips can generate several different frequencies for simultaneous use in the system, all controlled by a single micro (and possibly sharing one 32.768 khz crystal by chaining the clk32 pin to x in pin on the next device). in this case the clk in pin should be connected to v ss . the clock output on the clk out pin is continuous; the correct operating mode is automatically recognized by the sh3002. a microcontroller might not have a stop command. with the sh3002, this controller can do a ?simulated? stop by issuing an instruction to the sh3002 to stop the clock. this command is accepted only if the periodic interrupt / wakeup timer has started (otherwise, once the system is put to sleep, it would never wake up again). this mode of operations is only possible if the host processor is capable of correct operations with clock frequency down to zero, and keeps all of the internal ram alive while the clock is stopped. table 2. emi reduction with spectrum spreading setting en cfg1 cfg0 spreading bandwidth khz peak emi reduction (guaranteed) db peak emi reduction (measured) db 0 x x off 0 0 1 0 0 32 -3 -3 1 0 1 64 -6 -7 1 1 0 128 -9 -10 1 1 1 256 -12 -15
sh3002 microbuddy? system management copyright ?2002-2005 semtech corporat ion 9 v1.20 www.semtech.com low frequency (lf) oscillator system this module provides the 32 khz clock to all internal circuits and to the dedicated output pin, clk32. if enabled, the clk32 output continues normal operations when v dd is absent and backup power is available. just like the v bo value for the reset circuit, the default calibration values for the rc oscillator are loaded on power-up from the factory-programmed nonvolatile memory. they can be re-programmed at any time or they can be permanently prot ected from any changes by setting the lock flag or a write-protect flag. factory calibration brings the frequ ency of the rc oscillator within 3 % of the 32768 hz for the internal reference resistor, and 2% for the external 1 m ? 1% resistor, over the entire temperatur e and supply voltage range. the frequency of the rc oscillator can be tuned or modulated by varying the external reference resistor, which should be located as close as possible to r ref , pin 9. 9 rc oscillator 13 internal 32.768 khz clock external reference resistor 1 m ? 1% or variable internal r ref figure 5. simplified lf oscillator system 1 clk32 r ref 8 v ss v ss clk32 o n 4-bit value 6-bit value 4-bit value lock / unlock logic lock logic i nternal r ref o n from / to serial i/o
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 10 v1.20 www.semtech.com periodic interrupt / wakeup timer simple and versatile, the periodic interrupt / wakeup timer can be used to create very accurate recurring interrupts for use by the host micro. with some minimal software support from the host processor, it can also be used to create alarms, with practically unlimited duration. while the timer is running, the host processor can be halted, consuming no energy. the interrupt wakes up the processor, which can perform the requisite task and go back to sleep, until the next periodic interrupt. this mode of operation can achieve extremely low average power consumption. a 32-bit counter clocked by 32.768 khz, producing a minimum interval of 30.5 s and the maximum interval of 36.4 hours, creates the timer. after reset, the timer is stopped until the new value for the time interval is written into the 4-byte time interval register. when the l east significant byte (lsb) is written, the whole value is moved to the time interval latch, the counter is reset and starts to increment with the 32.768 khz clock. when the 32-bit comparator detects a match, an interrupt is generated and the counter is reset and starts the next timing cycle. although the counter cannot be written to, the current value from the counter can be read at any time. the whole 32-bit value is loaded into the 32-bit current timer value latch when the least significant byte is read. this prevents errors stemming from the finite time between the readings of indivi dual bytes of the current value. auxiliary functions voltage regulator pin v reg can be used as a nominal 2.20 v reference voltage or a supply source for small loads (<2 ma). a bypass capacitor might be nec essary between this pin and v ss if the load generates large current transients or a low ripple reference is required. 14 figure 6. periodic interrupt / wakeup timer io/i nt 32-bit time interval 32-bit counter 32-bit comparator 32-bit latch interrupt logic serial i/o r eset lsb msb 32-bit latch l oad l oad current timer value lsb msb 32.768 khz
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 11 v1.20 www.semtech.com interrupt and serial interface a single line is used to convey bi-directional information between the sh3002 and the processor, and as the interrupt line to the processor. the polarity of the interrupt signal is programmable. the sh3002 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. the bit rate is automatically determined by the sh3002. . at the fastest possible rate, a read or write access of a single byte from the register bank takes 5 s. the sh3002 contains 36 addressable registers located at 0x00?0x1f. some of these registers are accessed through a page operation. pin 14, io/int, is the serial communications inte rface and interrupt output pin. this pin is internally weakly pulled to the opposite of the programmed interrupt polarity. for example, if interrupt is programmed to be active low, this pin is weakly pulled to v dd when inactive. as shown in figure 7 , the sh3002 and the host communicate with serial data streams. the host always initiates communication. a data stream consists of the following (in this order): ? 3-bit start field ? 3-bit read/write code ? 5-bit address field ? 1 guard bit ? 8-bit data field ? 2 parity bits plus, for write streams only: ? 1 guard bit ? 2 acknowledge (ack) bits the 3-bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. the 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. this protects against early glitches that might otherwise put the interface into an invalid read or write access mode. the 5-bit address field contains the address of the register. a single guard bit gives the interface a safe period in which to change data direction. the value of a guard bit does not matter. the 8-bit data field is written to (read from) the register. two parity bits: the first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit is the inverse of the first. for write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write access. two guard bits are appended to the end of the access stream (read or write) . the host can not start the next access before receiving these bits. the interface is self-timed based on the duration of the start bit field, and communication can take place whenever clk out is active, either at 32.768 khz or at a higher frequency. if the host microcontroller is running synchronously to the clk out generated by the sh3002 (which should generally be the case), then a minimum of 4 clk out cycles per bit are required to maintain communication integrity. if the host?s serial interface is asynchronous to clk out , then a minimum of 52 cycles per bit are necessary. a maximum of 1024 clk out cycles per bit field is supported. table 3 displays the minimum and maximum bit periods for the serial communications for clk out frequencies of 16 mhz, 8 mhz, and 2 mhz. table 3 : minimum/maximum serial bit timing clk out frequency minimum bit period (host synchronous to clk out ) minimum bit period (host asynchronous to clk out ) maximum bit period 16 mhz 250 ns 3.25 s 63.9 s 8 mhz 500 ns 6.5 s 127 s 2 mhz 2 s 26 s 511 s interrupt interface the serial communications line to the sh3002 (pin 14, io/int) also serves as the interrupt to the host microcontroller. the polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the ipol_rctune register (r0x11). this pin is asserted for four cycles of clk out , and then returns to the inactive state. the interrupt line is used by the periodic interrupt/wake-up timer to interrupt the host when it reaches its end of count.
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 12 v1.20 www.semtech.com io/int timing scenarios 1. int disabled, up initiates write access. active high interrupt. ubuddyioout upioout a0 a4 xxx d0 d7 ... combinedio a0 a4 xxx d0 d7 ... ... 2. int active (high), up initiates write access ubuddyioout upioout combinedio xxx state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 idle xxx state if the interrupt did not get cleared, then it will activate again here 4. int disabled, up initiates read access ubuddyioout upioout a0 a4 xxx ... combinedio a0 a4 xxx d0 d7 ... ... state idle pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard2 idle d0 d7 ... p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 ack0 ack1 guard2 guard3 guard2 guard3 pendin g-start in t idle pendin g-start in t 3. int active (low), up initiates write access ubuddyioout upioout combinedio state if the interrupt did not get cleared, then it will activate again here a0 a4 xxx d0 d7 ... a0 a4 xxx d0 d7 ... ... xxx pre- start start post- start a0 a4 guard0 d0 d7 ... ... guard1 xxx p0 p1 p0 p1 p0 p1 ack0 ack1 ack0 ack1 rw0 rw1 rw2 guard2 guard3 pendin g-start in t idle pendin g-start in t ack0 ack1 rw0 rw1 rw2 guard3 figure 7: serial communication timing diagram
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 13 v1.20 www.semtech.com note: the sh3002 is esd-sensitive. description symbol min max units supply voltages on v dd relative to ground v dd -0.5 5.5 v input voltage on clk in , io/i nt , test v in 1 -0.5 v dd + 0.5 v input voltage on clk sel v in 2 -0.5 v reg + 0.5 v input current on any pin except v reg i in 1 10 ma input current on v reg i in 2 150 ma ambient operating temperature t op -40 85 oc storage temperature t stg -55 160 oc operating characteristics parameter symbol min typ max units notes case temperature t op ?40 +85 c supply voltage v dd 2.3 5.5 v supply current, clk out = 16 mhz* i dd 3 ma supply current, clk out = 8 mhz* i dd 1.8 ma supply current, clk out = 2 mhz* i dd 0.9 ma standby current, 32.768 khz rc oscillator** i sb 10 a clk32 disabled *note: assuming load on clk out < 20 pf **note: assuming temperature < 60oc electrical specifications absolute maximum ratings
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 14 v1.20 www.semtech.com operating characteristics of 32.768 khz rc oscillator parameter symbol min typ max units external 1 mohm referenced nominal frequency fext 32.768 khz internal 1 mohm referenced nominal frequency fint 32.768 khz clk32 duty cycle dc 40 60 % programmed frequency accuracy at 25c fst -1.5 +1.5 % absolute accuracy over temperature and supply (external 1 mohm) fde 2 % absolute accuracy over temperature and supply (internal 1 mohm) fdi 3 % frequency temperature stability (ext. 1 mohm) fse 100 ppm/c frequency temperature stability (int. 1 mohm) fsi 200 ppm/c power on startup time tst 70 s clk32 cycle to cycle jitter j 0.1 % operating characteristics of programmable reset parameter symbol min typ max units v dd switching threshold for min code (start-up default = 2.3 v) vbo(min) 2.27 2.3 2.33 v v dd switching threshold for max code vbo(max) 4.2 4.3 4.4 v v dd threshold resolution vres 33 mv v dd hysteresis vhys 50 mv falling v dd threshold switch delay td 2.5 s threshold digital-analog converter (dac) settling time tdac 4 ms minimum v dd for valid nrst vddmin 1 v
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 15 v1.20 www.semtech.com operating characteristics of the high-frequency oscillator (hfo) parameter symbol min typ max units minimum operating frequency (start-up default = 2 mhz) fmin 5.6 8 mhz maximum operating frequency fmax 16.8 21 mhz frequency resolution fres 2 khz programmed frequency accuracy at 25c fst -0.3 +0.3 % frequency drift over temperature and supply fdrift 0.5 % clk out cycle to cycle jitter (spread spectrum off) j 0.1 % startup time from standby tstart 2 s settling time to 0.1% after hf digitally-controlled oscillator (dco) code change tsett 10 s clk out duty cycle dc 40 60 % frequency temperature stability fts 100 ppm/c short term frequency stability fs 0.5 %/sec minimum spread spectrum range ssmin 32 khz maximum spread spectrum range ssmax 256 khz clk out rise/fall time (20 pf load) trf 3 ns clk out logic output low (4 ma load) vol 0.25 0.4 v clk out logic output high (4 ma load) voh -0.4 -0.25 ref v dd
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 16 v1.20 www.semtech.com free running hf dco frequency deviation over temperature for all frequencies -16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 0 2000 4000 -60 -40 -20 0 20 40 60 80 100 120 140 temp. oc ppm deviation internal 32.768 khz oscillator frequency over temperature 31800 32000 32200 32400 32600 32800 33000 33200 33400 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (oc) frequency (hz)
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 17 v1.20 www.semtech.com standby current over temperature (v dd = 5 v) 0.0 5.0 10.0 15.0 20.0 25.0 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (oc) v dd current (a) internal 32.768 khz standby current over v dd (temp. = 25oc) 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 v dd (v) v dd current (a) internal 32.768 khz
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 18 v1.20 www.semtech.com v dd current vs clkout frequency (v dd = 5.5 v, temp. = 25oc) 0 500 1000 1500 2000 2500 3000 3500 024681012141618 frequency (mhz) v dd current (a) operating v dd current over v dd (clkout = 16 mhz, temp = 25oc) 2000 2200 2400 2600 2800 3000 3200 2.5 3 3.5 4 4.5 5 5.5 v dd (v) v dd current (a)
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 19 v1.20 www.semtech.com free running hf dco short term frequency stability (clkout = 8 mhz) -400 -300 -200 -100 0 100 200 300 -500 500 1500 2500 3500 4500 5500 6500 time (seconds) ppm deviation fll locked hf dco jitter over jitter bandwidth (cl kout = 12.8 mhz) 10 100 1000 10000 100000 0.1 1 10 100 1000 10000 100000 jitter bandwidth (khz) rms jitter (ps)
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 20 v1.20 www.semtech.com package outline drawing mlp 3 x 3 mm 16 pins
sh3002 microbuddy? system management copyright ?2002-2005 semtec h corporation 21 v1.20 www.semtech.com for sales information and product literature, contact: semtech corporation human interface device (hid) and system management division 200 flynn road camarillo, ca 93012-8790 sales@semtech.com http://www.semtech.com/ (805)498-2111 telephone (805)498-3804 fax copyright ?2002-2003 semtech corporation. all rights reserved. semtech, the semt ech logo, microbuddy, buddy, and b are marks of semtech co rporation. all other marks belong to their respective owners. limited license granted: no warranties made this specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. any suggestions or comments by semtech concer ning use of this product are opinion only, and semtech makes no warranty as to results to be obtained in any specific app lication. a license is hereby granted to reproduce and distribute this specification for internal use only. no other license, expressed or implied to any other intellectual property rights is granted or intended hereby. authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of informat ion in this specification. authors of this specification al so do not warrant or represent that such implementation(s) will not infringe such rights.
filename: sh3002.doc directory: u:\working file\nathan\08_09_05 template: c:\documents and settings\lcarey\application data\microsoft\templates\normal.dot title: sh3002 microbuddy? data sheet subject: reset management and clock management support ic for microcontrollers author: semtech corporation keywords: comments: creation date: 1/24/2003 10:42 am change number: 75 last saved on: 8/8/2005 9:40 am last saved by: njohn total editing time: 260 minutes last printed on: 8/9/2005 2:34 pm as of last complete printing number of pages: 21 number of words: 4,388 (approx.) number of characters: 25,012 (approx.)

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